This invention relates to a semiconductor memory device wherein memory cells are integratedly allocated, more particularly, to a semiconductor memory device having multilayered bitline structure in which data lines (bitlines) for reading/writing data from/into memory cells are formed of two different wiring layers.
A dynamic random access memory (DRAM) is the most integrated device in the MOS-type semiconductor memory devices since each of the memory cells constituting the device has a relatively simple memory cell structure. Recently, the samples of 64 Mbit DRAM has been put into market, and some prototype of the 1 Gbit DRAM has been presented. The integration density of the DRAM has been enhanced not only by the improvement of the fine-processing technique, but also by constructing the memory cells three-dimensionally. The three-dimensional constitution of the device can remarkably reduce the area of each of the memory cells.
The three-dimensional memory cell structure can be roughly classified into a trench cell and a stack cell. As the stack cell, a COB (Capacitor Over Bitline) type stack cell in which a capacitor is formed above a bitline has been generally used.
FIGS. 1A and 1B respectively show a birds-eye view and a plan view of the conventional COB type stack cell, respectively. In the conventional COB type stack cell, the cell capacitor is formed above the bitline. Thus, a contact hole is formed between the adjacent bitlines such that a storage node as the lower electrode of a capacitor is connected with the active area therethrough. In this structure, the storage node shields the coupling capacitance between the bitlines, and the interference noise between the bitlines can be reduced, in comparing with the trench cell.
The COB type stack cell, however, is larger than the trench cell in the capacity between the bitline and the storage node. The total bitline capacity that is larger than that of the trench cell when the same number of cells in the trench cell are connected, and the power consumption necessarily increases in comparing with the trench cell. Further, when the capacity of the memory cell capacitor is determined at a predetermined level, so large amount of the total bitline capacity causes the decrease of the level of the signal input to the sense amplifier, thereby resulting the decrease of the reading margin.
The above-mentioned problems must be solved in such a manner that the power consumption is decreased to the equivalent level of the trench cell, and the level of the signal input to the sense amplifier is increased. To realize them, those skilled in the art would be easily think to further divide the bitlines to decrease the number of the cell connected to each of the bitlines. As the specific proposal, the multilayered bitline structure has been proposed.
FIG. 2 is a block diagram of a memory device having the multilayered bitline structure. In this structure, a plurality of lower bitlines (SBLs:Segment Bitlines, indicated in the diagram as BL1, /BL1, BL2, /BL2) each having a relatively short length are respectively shared by the upper bitlines (MBLs:Master Bitlines, indicated in the diagram as BL0, /BL0).
With this structure, the MBLs are shared by a plurality of blocks (BK1, BK2), and thus have a relatively long length. The MBLs are therefore generally formed of a metal wiring made from Al in consideration of the data transmission speed in the MBLs. The metal wiring cannot be easily formed thin in comparing with the wiring made from a material such as polyside, and has a thickness larger than that defined by the design rule. Further, the MBL is formed on the upper electrode of the capacitor of the COB type stack cell, and thus are not shielded by the storage node, in comparing with the SBLs. As a result, the capacity present between the adjacent MBLs will remarkably increase.
In addition, the MBLs are shared by a plurality of the SBLs as described above, and have the relatively long wiring length, the reading noise in the MBLs exceedingly increases therefor. The employment of the multilayered bitline structure in the COB type stack cell causes the problem of the noise between the bitlines which has been solved by employing the COB type stack cell, and the operation margin of the sense amplifier will be decreased thereby.